1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing techniques and, more particularly, to a method and apparatus for manufacturing a silicon semiconductor wafer.
2. Related Application
This application is related to application Ser. No. 844,783, filed Mar. 10, 1992, which is a continuation of application Ser. No. 638,775, filed Jan. 8, 1991, now abandoned, and entitled Single Wafer Regrowth of Silicon.
The present semiconductor integrated circuit technology is based predominantly on the element silicon. Silicon-based devices account for a significantly large percentage of semiconductor devices manufactured. One well-known technique of fabricating silicon based integrated circuits involves what is commonly referred to as the metal-oxide-semiconductor (MOS) technology. In the practice of MOS technology, silicon is used as a base substrate, wherein doped regions are formed in the substrate and various layers and lines are formed overlying the substrate to fabricate an integrated circuit "chip".
In a typical semiconductor integrated circuit fabrication process, devices are constructed onto a preformed silicon wafer. These wafers are typically flat and circular in shape. The diameter of the wafers vary from approximately four (4) inches to eight (8) inches. By utilizing a number of various processing techniques, which may include doping, implanting, depositing, etching, to name a few, a number of completed chips are formed on a silicon wafer. Subsequently, the wafer is cut to separate each independent chip and packaged for use.
The semiconductor technology has evolved and continues to evolve to reduce the size of each transistor formed on the substrate. The reduction of the dimensional geometry of the transistor, as well as the lines interconnecting the transistors, has permitted more devices to be fabricated per unit area on the silicon wafer. Furthermore, equipment and process technologies have evolved to permit larger diameter wafers to be fabricated in order to increase the number of chips which can be manufactured on a given wafer.
Although the silicon semiconductor technology has evolved significantly since its inception, the technique for the manufacturing of the silicon wafer itself has not evolved appreciably in comparison. Substantially all of present day silicon semiconductor wafers are manufactured by a well-known crystal growing technique commonly referred to as the Czochralski (CZ) technique. The CZ technique, developed as early as the 1920's, is still the preferred technique today.
The CZ process utilizes an apparatus having a crucible in which chunks of high-purity polysilicon material is placed. An attendant heater melts the silicon material such that the liquid form of the silicon is contained in the crucible. Subsequently, an elongated shaft, which contains a seed crystal, is lowered into the crucible. Typically, the seed is comprised of a monocrystalline silicon material which is used to grow the monocrystalline silicon from the liquid polysilicon. Under a finely controlled process, the shaft is slowly raised. As the shaft is raised out of the crucible, the liquid polysilicon adheres to the shaft and is also pulled upward out of the crucible. As the liquid silicon cools and hardens, the process provides for the crystallization of the silicon being drawn upward and outward from the crucible. Due to the presence of the monosilicon seed, monocrystalline crystal growth occurs as the silicon material is pulled out of the crucible. When the crystal growing process is completed, a solid cylinder of monocrystalline silicon is obtained. Then, this cylinder of silicon is cut and formed to provide a number of given diameter silicon wafers. The CZ technique is well-known in the prior art and is described in detail in VLSI Technology; S. M. Sze, McGraw Hill, 1988, particularly in Chapter 1, entitled "Crystal Growth and Wafer Preparation" by C. W. Pearce.
Although the CZ technique is an adequate technique for the production of silicon wafers, it is a batch process. Further, it has a number of disadvantages which makes this CZ method somewhat inefficient. For example, a significant amount of processing time is required to grow the crystal onto the shaft which is pulled upward and outward from the crucible in a controlled environment. A typical processing time is approximately one to two days to grow a cylinder of silicon having a length of one meter and a diameter of 200 mm or more. The subsequent cutting of the silicon cylinder also adds processing time. This cutting of the silicon cylinder requires a specialized cutting tool and typically results in more than fifty percent of the material being wasted.
Accordingly, it is appreciated that an improved technique of manufacturing silicon wafers over the Czochralski method is desired. The present invention overcomes many of the disadvantages of the prior art CZ technique and provides for a casting of a single silicon wafer instead of the batch manufacturing process of the CZ technique.